基于VCCT理论的芯片多顶针剥离工艺参数优化

Optimization of chip multi-ejector stripping process parameters based on VCCT theory

针对芯片在拾取过程中易碎裂的问题,采用虚拟裂纹闭合法对多顶针工艺拾取芯片的过程进行动力学建模和仿真。首先建立了芯片-胶层-蓝膜复合模型结构;然后进行了硅片-蓝膜单轴拉伸实验,确定了模型的关键参数;最后通过模拟不同工艺参数,包括顶针间距和胶层材料的变化,对剥离过程中芯片上的最大应力变化进行了深入的分析。仿真结果显示,在芯片剥离过程中,芯片中心区域出现了明显的应力集中。减小顶针间距可以有效缓解芯片中心区域的应力集中现象。此外,选择具有较低临界断裂能的胶层材料可以减小剥离过程中芯片所受的应力。最终结果为多顶针拾取芯片工艺的参数选择提供了参考价值,有助于提高芯片拾取的可靠性。

In order to prevent the chips from chipping during pickup,the virtual crack closure method was used to dynamically model and simulate the process of picking up chips in the multi-ejector pin process.First,the chip-adhesive layer-blue film composite model structure was established.Then the key parameters of the model were determined through the silicon wafer-blue film tensile experiments.Finally,the stress variation on the chip during the peeling process were analyzed by simulating different process parameters,including ejector pin spacing and adhesive layer materials.The simulation results indicate that the concentration of the stress occurs in the central area of the chip during peeling.Reducing the distance between ejector pins and the critical fracture energy of the adhesive layer can alleviate the stress concentration.The results provide the reference for the parameter selection of the multi-ejector pin pick-up chip process,which is helpful to improve the reliability of chip pick-up.