栅场板型Ga_(2)O_(3)MOSFET器件单粒子烧毁仿真研究

Simulation of Single Event Burnout in Gate-Field-Plated Ga_2O_(3) MOSFET Devices

设计了1种抗单粒子烧毁(single event burnout,SEB)效应能力较强的栅场板型结构Ga_(2)O_(3)MOSFET器件,并与平面型结构进行了对比,采用基于计算机辅助设计(technology computer aided design,TCAD)的商用半导体器件仿真模拟软件研究了2款器件发生SEB前后内部载流子浓度、电流密度等电学参数分布特性,深入研究了Ga_(2)O_(3)MOSFET器件发生SEB的机理及引入栅场板结构后SEB阈值电压增大的原因。在此基础上,对器件的结构进行优化,获得了抗SEB性能较好的结构参数。研究结果表明:2款Ga_(2)O_(3)MOSFET器件发生SEB的机理都是由于其内部难以实现p型掺杂,主要是电子导电,当器件处于关断状态时,栅极下方会形成耗尽区,而重离子入射碰撞离化产生的电子在耗尽区的积累会对衬底层中电子通道的开启具有显著影响。当器件发生SEB时,源极的电子会通过V型的电子通道流向漏极,使得器件发生短路,产生大电流并烧毁;与平面型Ga_(2)O_(3)MOSFET器件相比,引入栅场板结构的器件在沟道区域的峰值电场强度由2.9 MV·cm^(-1)降低至1.7 MV·cm^(-1),从而降低了重离子入射器件后,碰撞离化产生载流子的速率,另一方面,引入栅场板结构也扩大了耗尽区的范围,使得栅极的控制能力增强,将器件发生SEB的阈值电压从110 V提升至340 V;最后通过仿真优化SiO_(2)钝化层的厚度以及栅场板的长度,得到了抗SEB能力更强的器件结构参数,进一步将器件SEB阈值电压提升至380 V。

A gate field plated Ga_2O_(3) MOSFET device with enhanced resistance to single event burnout(SEB) is designed and compared with planar Ga_2O_(3) MOSFET devices.By utilizing commercial semiconductor device simulation software based on technology computer aided design(TCAD),the distribution characteristics of internal carrier concentration,current density,and other electrical parameters before and after SEB are studied for both devices.The mechanism of SEB in Ga_2O_(3) MOSFET devices and the reason for the increased SEB threshold voltage after introducing the gate-field-plated structure are deeply studied.Based on this analysis,the device structure is optimized to obtain better resistance to SEB.The results show that the SEB mechanisms in both Ga_2O_(3) MOSFET devices are primarily due to difficulties in achieving p-type doping internally,resulting in electron conduction.When the device is in the off-state,a depletion region forms beneath the gate,and the accumulation of electrons generated by heavy ion collision ionization significantly affects the opening of the electron channel in the substrate layer.During SEB occurrence,electrons from the source flow to the drain through a “V”-shaped electron channel,causing a short circuit and resulting in high current flow and device burnout.Compared to planar Ga_2O_(3) MOSFET devices,the introduction of the gate-field-plated structure reduces the peak electric field intensity in the channel region from 2.9 MV·cm~(-1) to 1.7 MV·cm~(-1),thereby decreasing the rate of carrier generation due to collision ionization after heavy ion irradiation.Additionally,the gate field plate Ga_2O_(3) MOSFET device enlarges the depletion region,enhancing the control capability of the gate,and increasing the SEB threshold voltage from 110 V to 340 V.Finally,through simulation optimization of the SiO_(2) passivation layer thickness and the gate field plate length,device structure parameters with stronger resistance to SEB are obtained,further increasing the SEB threshold voltage to 380 V.