56 Gbit/s低功耗分数间隔FFE PAM4 SerDes发射机设计

Design of 56 Gbit/s Low-Power PAM4 SerDes Transmitter with Fractionally-Spaced FFE

采用65 nm CMOS工艺设计了一款用于高速芯片互联的四电平脉冲幅度调制(PAM4) SerDes发射机。该发射机主要由最高有效位通道和最低有效位通道、时钟产生路径、前馈均衡模块、接口驱动电路等构成。采用一种无锁存的并串转换技术,以降低功耗;采用一种分数型前馈均衡技术,获得了超出奈奎斯特频率点的频率补偿峰值,从而扩展频率补偿范围,使输出信号能更好地适应信道。此外,采用带预充电结构的4∶1并串转换器,减小电荷共享效应对电路的影响。仿真结果表明,在1 V电源电压下,整体电路能实现56 Gbit/s PAM4输出信号,输出眼图清晰,且获得电平失配率为93.1%的高线性度,输出摆幅达到480 mV,功耗为75 mW。

A four-level pulse amplitude modulation(PAM4)SerDes transmitter for high-speed inter-chip interconnections was designed using a 65 nm CMOS technology.The entire transmitter comprises most significant bit(MSB)channels,least significant bit(LSB)channels,clock generation paths,feedforward equalization modules,and interface drivers.A latchless parallel-to-serial conversion technique is used to minimize power consumption.A fractional feedforward equalization technique is employed to extend the frequency compensation range beyond the Nyquist frequency to enhance the adaptability of the output signal to the channel.Additionally,a 4∶1 parallel-to-serial converter with pre-charge ability is utilized to mitigate the impact of the charge-extraction effects.Simulation results demonstrate that the designed transmitter achieves a 56 Gbit/s PAM4 output signal at a supply voltage of 1 V,a clear output eye image,a high-linearity of the level mismatch ratio(RLM)of 93.1%,an output swing of 480 mV,and a power consumption of 75 mW.