微型组合导航SIP芯片的PDN电热协同仿真与优化

PDN electro-thermal co-simulation and optimization of micro integrated navigation SIP chip

随着SIP芯片逐步小型化和集成化,导致芯片对PDN的直流压降、电流密度以及系统的温升控制要求越来越高.本文通过改变载流导体的面积来改善直流压降和电流密度过高的问题,同时针对芯片温升研究通过合理优化热过孔阵列的孔径、过孔数量以及镀铜厚度来减小热阻以达到控制芯片温升的目的.仿真结果表明,增加载流导体的面积能有效降低直流压降和电流密度,且还留有很大的裕量;而热过孔阵列的合理布局能有效控制芯片温升,从而提升了芯片的功能和可靠性.

With the gradual miniaturization and integration of SIP chips,the chip has higher requirement for DC voltage drop,current density of PDN and the temperature rise control of the system.In this paper,DC voltage drop and current density is improved by changing the area of the current-carrying conductor,and at the same time,studies are made on the chip temperature rise which is controlled by reasonably optimizing the aperture of thermal-via array,the number of vias and the thickness of the copper plating to reduce the thermal resistance.Simulation results show that increasing the area of the current-carrying conductor can effectively reduce DC voltage drop and current density,still with a large margin left,and that the reasonable layout of thermal-via array can effectively control the chip temperature rise,thus improving the function and reliability of the chip.