CAN总线错误检测系统设计与分析

Design and analysis of CAN bus error detection system

为尽早发现CAN总线上数据传输时发生的错误、及时修复故障节点,设计了一种以FPGA为核心控制器的CAN总线错误检测系统。系统使用Verilog硬件描述语言编写CAN控制器,实现CAN总线协议的解析功能。分析总线上发生错误的类型,能够对位错误、填充错误、校验错误、格式错误和应答错误进行检测。检测结果以固定格式封装于UDP数据段,通过UDP驱动程序发送至上位机进行显示。模拟CAN通信环境对系统进行测试,结果表明,系统能够正确检测出CAN总线上发生的错误,对保障总线通信的稳定性方面具有一定的应用价值。

To detect the error occurring during data transmission on the CAN bus as early as possible and fix the failure node promptly,a CAN bus error detection system with FPGA as the core controller is studied and designed.The system uses Verilog HDL to design the CAN controller to realize the parsing function of the CAN bus protocol.Analyzing the types of errors that occur on the bus can detect bit errors,padding errors,validation errors,format errors,and answer errors.The detection results are encapsulated in the UDP data segment in a fixed format and sent to an upper computer for display through the UDP driver.The experiment in simulated CAN communication environment shows that the system can accurately detect the errors on the CAN bus,indicating its potential application value in guaranteeing the stability of the bus communication.