高增益高驱动能力的基准电压缓冲芯片的设计

Design of reference voltage buffer chip with high-gain and high-driving capability

为了解决当前CMOS基准电压缓冲器在驱动大电容负载电路时所面临的可靠性问题和性能瓶颈,提出一种高增益高驱动能力的基准电压缓冲芯片。该芯片采用CMOS缓冲放大器,结构包括折叠式共源共栅输入级、轨至轨Class AB输出级和推挽输出缓冲级。设计中加入了修调电路、Clamp电路及ESD防护电路。芯片面积为2390μm×1660μm。在SMIC 0.18μm CMOS工艺下进行了前仿真、版图绘制及Calibre后仿真。前仿结果显示:当负载电容为10μF时,电路实现了126 dB的高开环增益和97°的相位裕度,同时PSRR超过131 dB,噪声为448 nV/Hz@100 Hz及1 nV/Hz@100 Hz。后仿结果与前仿结果基本一致。总体结果表明,该电路具有高增益、高电源抑制比及低噪声等特点,同时拥有很高的输出驱动能力。因此,所提出的基准电压缓冲芯片可以用于驱动如像素阵列等具有大电容负载的电路。

In allusion to the reliability issues and performance bottlenecks encountered by the current CMOS reference voltage buffer when driving large-capacitance load circuits,a reference voltage buffer chip with high gain and high driving capacity is proposed.The chip employs a CMOS buffer amplifier,featuring a folded cascode structure at the input stage,a rail-to-rail Class-AB structure at the output stage,and a push-pull output buffer stage.In the design,the trimming circuits,Clamp circuits,and ESD protection circuits are incorporated.The chip area is 2390μm×1660μm.The pre-simulation,layout design,and post-simulation with Calibre are conducted under the SMIC 0.18μm CMOS process.The pre-simulation results demonstrate that with a load capacitance of 10μF,the circuit can realize a high open-loop gain of 126 dB,a phase margin of 97°,and a PSRR exceeding 131 dB.The noise levels are 448 nV/Hz@100 Hz and 1 nV/Hz@100 kHz.The post-simulation results are consistent with the pre-simulation results.The overall results demonstrate that that the circuit has characteristics such as high gain,high power suppression ratio,and low noise,as well as high output driving capability.Therefore,the proposed reference voltage buffer chip can be utilized to drive circuits such as pixel arrays with large capacitive loads.