基于FPGA的基带信号发生器IP核设计与验证

Design and Verification of IP Core of Baseband Signal Generator Based on FPGA

雷达系统中信号收发模块需要内部产生基带信号,面对这一需求设计了一种基于直接数字频率合成(DDS)技术且能自定义起始斜率和起始频率的基带信号发生器IP核。该IP核的输出频率可根据线性调频信号的特征进行设计,根据正弦信号的对称性,结合相位截断法和CORDIC算法设计了DDS模块的正余弦查找表,减少了资源的占用率,降低了功耗,提高了运算速度。仿真结果显示,设计的IP核可以正常输出不同频率的正余弦波形以及线性调频信号波形,并且能够实现自定义调整,具有较高的灵活性。相较于通过多个DDS叠加生成混频波形,该IP核占用资源更少,且具有实用价值。

The signal transceiver module in the radar system needs to generate baseband signals internally.To meet this requirement,the baseband signal generator IP core is designed based on direct digital frequency synthesis(DDS)technology,enabling customization of starting slope and starting frequency.The output frequency of the IP core is designed according to the characteristics of linear frequency modulation signals.Combining phase truncation method with CORDIC algorithm,the sine-cosine lookup table of the DDS module is designed to reduce resource occupancy and power consumption and enhance operational speed.Simulation results demonstrate that the designed IP core can normally output sine and cosine waveforms at different frequencies as well as linear frequency modulation signal waveforms,and can realize customizable adjustments,and show high flexibility.Compared to generating mixed-frequency waveforms through multiple DDS superposition,this IP core occupies fewer resources while maintaining practical value.