一种旁路机制下的低功耗片上网络功率门控设计

A Low-Power Network-on-Chip Power-Gating Design with Bypass Mechanism

随着技术尺寸的缩小,静态功耗在片上网络(NoC)的功耗开销中占据主导地位。功率门控作为一种通用的功耗节约技术,将NoC中空闲模块关闭以降低静态功耗。然而,传统的功率门控技术带来了诸如数据包唤醒延迟,盈亏平衡时间等问题。为了解决上述问题,该文提出代替功率门控路由器进行数据包传输的分区旁路传输机制(PBTI),并基于该旁路机制设计了低延迟低功耗的功率门控方案。PBTI使用相互独立的旁路分别处理东西方向传输的数据包,并在旁路内部使用公共的缓冲区以提高缓冲区利用率。PBTI可以在路由器断电时实现数据包的注入、传输和弹出。即使网络中所有的路由器均处于功率门控状态,数据包也可以从源节点传输到目的节点。当流量增大超过PBTI的传输能力时,路由器以列为单位进行统一的唤醒。实验结果表明,与不使用功率门控的NoC相比,所提方案降低了83.4%的静态功耗和17.2%的数据包延迟,同时只额外增加了6.2%的面积开销。相较于常规的功率门控方案该文功率门控设计实现了更低的功耗和延迟,具有显著的优势。

Static power consumption dominates the power overhead of Network-on-Chip(NoC)as the technology size shrinks.Power gating,a generalized power saving technique,turns off idle modules in NoCs to reduce static power consumption.However,the conventional power gating technique brings problems such as packet wake-up delay,break-even time,etc.To solve the above problems,the Partition Bypass Transmission Infrastructure(PBTI),which replaces the power gated router for packet transmission,is proposed in this paper,and a low-latency,low-power power gating scheme has been designed based upon this bypass mechanism.PBTI uses mutually independent bypasses to handle east-west packets separately,and uses common buffers within the bypasses to improve buffer utilization.PBTI can inject,transmit,and eject packets when the router is powered off.Packets can be transmitted from the source node to the destination node even if all routers in the network are power gated.When the traffic increases beyond the transmission capacity of PBTI,the routers perform a uniform wake-up in columns.Experimental results show that compared to the NoC without power gating,the scheme in this paper reduces 83.4% of static power consumption and 17.2% of packet delay,while adding only 6.2% additional area overhead.Compared to the conventional power gating scheme the power gated design in this paper achieves lower power consumption and delay,which is a significant advantage.