压阻式压力传感器芯片悬空型无引线封装结构的设计与实验

Design and Experiments of Suspended Leadless Packaging Structure for Piezoresistive Pressure Sensor Chips

传感器的无引线封装技术取消了传统的引线键合连接,因而在极端环境下,具有耐高温、抗冲击能力强等特点,有广阔的发展前景。但在常规无引线封装结构中,芯片与玻璃基座烧结固连,会受到高温热固耦合下的热应力影响,进而降低测量精度。针对这一问题,以压阻式压力传感器芯片作为封装对象,提出了一种芯片悬空型无引线封装结构,对其封装材料的选择进行了研究并对整体热应力分布及大小进行了仿真分析;通过实验探究了封装结构中金属电极-导电银浆-金属插针电学互连通道在高温环境下的电学稳定性和力学强度;对采用该封装结构的压力传感器样品进行了输出和温度性能测试。结果表明,该封装结构整体所受热应力显著低于常规结构;电学互连通道的接触电阻远小于芯片压敏电阻,高低温循环条件下其阻值变化小于14Ω;高低温冲击后其拉伸破坏拉力在1.2 N以上;传感器样品输出电压线性度良好,在25~225℃内最大热零点漂移小于0.01%FS/℃,最大热满量程输出漂移小于0.20%FS/℃,相比于常规无引线封装结构显著减小了传感器热零点漂移,验证了该封装结构的可行性,为解决常规无引线封装结构中芯片热应力自释放问题提供了一个新的研究思路。

Due to the elimination of traditional wire bonding connections,the leadless packaging technology for sensors exhibits high-temperature resistance and strong impact resistance in extreme environments,offering broad development prospects.However,in conventional leadless packaging structures,the chip is sintered and bonded to a glass substrate,which is affected by thermal stress under high-temperature thermosetting coupling,thereby reducing measurement accuracy.To address the issue,a chip-suspended leadless packaging structure for piezoresistive pressure sensor chips was proposed.The packaging material selection was studied,and the overall thermal stress and its magnitude were simulated and analyzed.Experiments were conducted to explore the electrical stability and mechanical strength of the electrical interconnection channel composed of metal electrodes,conductive silver paste,and metal pins in high-temperature environments.Output and temperature performance tests were carried out on sensor samples adopting the packaging structure.Results show that the overall thermal stress of the packaging structure is significantly lower than that of the conventional structure.The contact resistance of the electrical interconnection channel is much lower than the piezoresistances of chips,with a resistance change in high-and low-temperature cycles being less than 14Ω.After high-and low-temperature shocks,the tensile failure force exceeds 1.2 N.The output voltage of the sensor sample exhibits good linearity,with a maximum thermal zero drift of less than 0.01%FS/℃and a maximum thermal full-scale output drift of less than 0.20%FS/℃within 25~225℃.Compared to conventional leadless packaging structures,the thermal zero drift of the sensor is significantly reduced,verifying the feasibility of the packaging structure and providing a new research approach to solve the issue of self-release of chip thermal stress in conventional leadless packaging structures.