基于后量子密码算法的安全SoC芯片设计

Design of security SoC based on post-quantum cryptography algorithm

后量子密码算法已经成为当前安全领域的研究热点。本文通过对NIST后量子密码算法竞赛候选的Saber算法进行研究,提出一种基于后量子密码算法的安全SoC芯片设计方案。该方案首先分析算法的硬件架构,优化矩阵运算和数值拼接等操作提升硬件效率,采用二次验证方式加强算法解密过程的安全性;然后,设计Hash随机数拓展生成模块、加解密模块和数据存储器以及随机数种子生成器,完成Saber算法的硬件IP核;其次,在RISC V处理器、总线和接口电路的基础上,结合时钟门控技术降低功耗,设计基于后量子密码算法的安全SoC芯片。实验结果表明,所设计的安全SoC芯片面积为2.6 mm^(2),等效逻辑门数为90k,芯片内核面积占比为75.2%,PAD面积占比为24.8%,芯片功耗为9.467 mW。

Post-quantum cryptography has become a research hotspot in the current security field.In this paper,a secure SoC design scheme based on post-NIST quantum cryptography is proposed by studying Saber algorithm,which is a candidate of post-NIST quantum cryptography competition.The scheme firstly analyzes the hardware architecture of the algorithm,optimizes operations such as matrix operation and numerical splicing to improve hardware efficiency,and uses secondary verification to enhance the security of the decryption process of the algorithm,design Hash random number expansion generation module,encryption and decryption module and data storage and random number seed generator to complete the Saber algorithm hardware IP Core.On the basis of RISC-V processor,bus and interface circuit,a secure SoC based on post-quantum cryptography is designed with clock gating technology.The experimental results demonstrate that the area of the designed security SoC chip is 2.6 mm^(2),with an equivalent logic gate count of 90k.The chip core area accounts for 75.2%,the PAD area accounts for 24.8%,and the chip power consumption is 9.467 mW.