一种14位80 MS/s流水线型A/D转换器设计

Design of a 14-bit 80 MS/s pipelined A/D converter

基于SMIC 0.18μm CMOS工艺,设计了一种14位80 MS/s的流水线型A/D转换器(ADC)。为了降低ADC整体功耗,首级电路采用2.5 bit无采样保持(SHA-less)结构。进一步,基于套筒式共源-共栅结构提出了一种改进型运放,通过复制尾电流反馈技术和增益提高技术的应用提升了运放的速度和增益,且功耗较低。比较器仅采用动态锁存器以减小级间延迟。还采用了栅压自举开关降低开关导通电阻,提高采样网络带宽和线性度。芯片测试结果表明,在1.8 V电源电压、采样频率为80 MHz的条件下,输入信号频率分别为10 MHz和70 MHz时,ADC的动态参数性能相差不大。其中,输入信号频率为70 MHz时,信噪失真比(SNDR)为72.2 dB,无杂散动态范围(SFDR)为85.82 dB,有效位数(ENOB)为11.7 bit,品质因数(FoM)为0.38 pJ/(conv·step)。

Based on the SMIC 0.18μm CMOS process,a 14 bit 80 MS/s pipelined A/D converter(ADC)is designed.In order to reduce the overall power consumption of the ADC,a 2.5 bit sample-and-hold-less(SHA-less)structure is adopted to reduce noise and power consumption.Further,an improved op-amp based on a telescopic cascode structure is proposed,which improve the speed and gain of the op-amp with lower power consumption by replica-tail feedback technique and gainboost technique.Only a dynamic latch is adopted in the comparator to reduce inter-stage delay.A gate-voltage bootstrap switch is also employed to reduce the switch on-resistance and improve the sampling network bandwidth and linearity.The chip test results show that the dynamic parameter performance of the ADC does not differ much when the input signal frequency is 10 MHz and 70 MHz,respectively,under the condition of 1.8 V supply voltage and sampling frequency of 80 MHz.In particular,the signal-to-noise distortion ratio(SNDR)is 72.2 dB,the spurious-free dynamic range(SFDR)is 85.82 dB,the effective number of bits(ENOB)is 11.7 bit,and the quality factor(FoM)is 0.38 pJ·conv−1·step−1 when the input signal frequency is 70 MHz.