大规模硅基光电子集成芯片技术与挑战(特邀)

Technologies and Challenges of Large-Scale Silicon Photonic Integrated Circuit(Invited)

从硅基光电子芯片在近年来的发展现状入手,对大规模集成背景下的器件与系统性能匹配发展脉络进行综述,同时从设计人员以及生产制造的角度,对面向规模芯片出货的生产模式、设计制造全流程方法以及一致性工程等关键技术进行分析,并进一步讨论未来硅基光电子集成芯片的大规模推广应用前景。

Significance The development trend of silicon photonic integrated circuits(SiPICs)in recent years parallels the historical evolution of integrated circuits(ICs).In terms of chip integration scale,digital ICs had achieved a scale of 106 before 1990,and by 2020,they had advanced to ultra-large scale integration ranging from 1010 to 1011.Over decades,the development of digital ICs has adhered to“Moore’s Law”,where significant reductions in operating voltage due to transistor miniaturization have enhanced efficiency and integration.Smaller chip sizes allow for more chips to be produced from the same-sized wafer,thus reducing marginal costs.From the perspective of signal carrier properties,the optical carrier transmission process in SiPIC exhibits typical analog signal characteristics,akin to analog ICs that focus on processing high-frequency continuous signals.System performance emphasizes factors like signal-to-noise ratio,distortion,power consumption,and stability.In terms of integration density limits,SiPIC shares similarities with analog ICs.Unlike digital ICs,analog ICs do not always benefit from transistor miniaturization as they do not strictly follow Moore’s Law for iteration.Smaller transistor sizes can sometimes compromise the overall performance and operational stability of high-voltage power management chips.Traditionally,analog ICs have also leaned towards mixed-signal technology development.For SiPIC,the challenge lies in the optical diffraction limits that make it difficult to reduce the width of optical waveguides below 100 nm.Additionally,achieving nanoscale modulation devices faces material constraints,posing hurdles to increasing integration density.For downstream applications,there exists a significant correlation between larger SiPIC chip scales and better system performance.In optical communication transceiver modules,scaling up in parallel can increase the number of transceiver channels,thereby strengthening overall module throughput.In photon AI computing,increased parallelism allows for more channels,facilitating larger convolutional kernel computations and higher data throughput.Longer cascaded links can also support a broader range of matrix calculations,boosting data fitting capabilities.In Lidar applications,augmenting the number of phased array antennas effectively enhances beam quality and directional accuracy.Therefore,the expansion in device scale,coupled with higher signal quality requirements and limited potential for miniaturization,poses unique challenges for large-scale integration of silicon-based optoelectronic chips,distinct from those encountered in traditional digital or analog circuits.Progress We introduce technical solutions for the entire process of scalable design and manufacturing,along with the iterative processes between fabs and design customers.We then analyze the fundamental integrated devices in SiPIC from the perspective of on-chip large-scale device integration,including IO switching devices,transmission devices,passive control devices,active control devices,light sources,and detectors.Furthermore,we examine the theoretical limit of integration scale for silicon optoelectronic devices at the current technological level.The essence of scaling SiPIC lies in the reuse,modification,and combination of device units.Designers at the link level focus on optimizing performance,footprint,process sensitivity,and environmental robustness through rational architectural design.Using SiPIC AI and Lidar chip design as examples,we analyze common SiPIC AI design architectures and device layout methods,discuss the characteristics and limitations of waveguide routing and metal wiring in PIC chips,and explore the challenges and prospects of achieving large-scale integration of SiPIC at the circuit level.The number of components in SiPIC chips has reached the order of 104,including optical and electrical components,as well as electrical IO ports,also numbering around 104.The yield rate issue,encompassing the reliability of numerous optoelectronic components during manufacturing and their consistency within and across chips and wafers,is crucial for mass production feasibility and lowering production costs.Therefore,we analyze the manufacturing challenges of electrical and optical components in chip manufacturing from the perspective of large-scale production and discuss the development trajectory for large-scale manufacturing of SiPIC.Conclusions and Prospects SiPIC demonstrates higher upper limits in terms of operating frequency,channel multiplexing,and anti-interference compared to traditional ICs,fostering complementary development with them.However,achieving larger scale integration and broader application support still lacks systematic automated design tool support.There remain numerous engineering challenges related to material systems,process flows,and packaging testing that need addressing to gradually reduce procurement costs and mitigate application risks for downstream demands.In the short term,increasing SiPIC integration can be achieved by reducing device sizes and optimizing device performance.Through reverse design,generative adversarial networks,and other advanced optimization algorithms,the design space can be expanded to achieve superior device performance with smaller footprints.Collaborative optimization algorithms for process flows and device design can establish processing conditions at the design stage,narrowing the performance gap between design and fabrication and strikingly improving manufacturing yield.Moreover,the introduction of new process platforms and the integration of new materials heterogeneously—such as graphene,plasmonics,and two-dimensional van der Waals heterostructures—can offer new solutions for shrinking device sizes and refining the optical and electrical properties of current devices.In the long term,due to optical diffraction limits and spot size constraints,the device integration density of SiPIC will encounter inherent limits.Future developments may parallel analog ICs,leveraging advantages in signal quality and rate to complement digital IC functions.This convergence aims to optimize system-wide power consumption,performance,and cost control.