摘要
针对离散小波变换的提升算法进行研究和优化,提出一种基于5/3的二维离散小波变换的硬件架构。离散小波变换整体工作过程都采用了并行输入输出结构,使用内部RAM对计算过程中间变量进行暂存。将三级流水线结构运用到列滤波器和行滤波器的设计上,设计出逻辑较为简单且内存较小的转置单元。减少外部RAM存储空间,采用5个RAM对小波系数进行存储。通过实验,在XILINX KC705型现场可编程逻辑门阵列上实现无损压缩系统,对4幅图像进行压缩,压缩比在1.3~2之间。本设计节约了硬件资源消耗,缩小了关键路径延时,DWT模块工作频率可达219 MHz,在实际应用中具有一定的技术优势。
A hardware architecture for 2D discrete wavelet transform(DWT)based on the 5/3 lifting scheme is proposed.The architecture employs a parallel input-output structure for the entire DWT process,using internal RAM to temporarily store intermediate variables during computation.A three-stage pipeline structure is applied to the design of both row and column filters,and a transposition unit with simple logic and small memory is designed.The external RAM storage space is reduced,and 5 RAMs are used to store wavelet coefficients.Through experiments on a XILINX KC705 FPGA,a lossless compression system is implemented,and four images are compressed with compression ratios ranging from 1.3 to 2.The design saves hardware resources,reduces critical path delay,and the DWT module can operate at a frequency of up to 219 MHz,demonstrating certain technical advantages in practical applications.
作者
沈鸿媛
郝亚喆
SHEN Hongyuan;HAO Yazhe(School of Information Science and Engineering,Northeastern University,Shenyang 110819,China)
出处
《微处理机》
2024年第5期13-16,共4页
Microprocessors
基金
基于二维纳米材料表面等离子共振效应传感的研究(N2304018)。
关键词
离散小波变换
无损压缩
VLSI设计
Discrete wavelet transform
Lossless compression
VLSI design