基于PDN阻抗的电路板级电源完整性仿真分析与优化

Simulation Analysis and Optimization of Board-Level Power Integrity Based on PDN Impedance

目前IC芯片呈现高速、高密度、低压大电流发展趋势,电源完整性(PI)问题日益突出,不合理的电源完整性设计将导致去耦电容器数量增多且达不到理想效果。文章针对电源完整性核心问题,即电源分配网络(power distribution network,PDN)进行研究,提出一种基于目标阻抗的去耦电容器选择和安装的设计方法。首先从全频段PDN组成出发,分析电路板级电容等效模型、不同电容器组合去耦效果及优化方法;接着,针对电容器安装过程中引入的寄生电感对电容器去耦效果的影响,重点分析了电容器安装走线长度、宽度及过孔距离对回路寄生电感的影响;最后结合实际单板进行了PDN阻抗仿真优化。结果显示,优化后的PDN可以满足目标阻抗要求,减少了15%的电容器数量,降低了成本;同时改善了电源的完整性,提高了单板可靠性。

As integrated circuit(IC)chips evolve toward high speed,high density,low voltage,and high current,ensuring power integrity(PI)has become increasingly prominent.Inadequate power integrity design can lead to deviations from the ideal performance even with more decoupling capacitors.This paper presents a design methodology for the selection and placement of decoupling capacitors based on target impedance,concentrating on the core aspect of power integrity:the power distribution network(PDN).The study began with analyses related to an equivalent model representing board-level capacitance,the decoupling effects of different capacitor combinations,and relevant optimization methods based on the full-band PDN composition.Subsequent investigation explored the influence of trace lengths,trace widths,and via hole intervals for capacitor placement on the parasitic inductance of circuits,in view of the impact of parasitic inductance introduced during the capacitor placement process on the decoupling effect of capacitors.Additionally,simulations were conducted to optimize PDN impedance based on real printed circuit boards(PCBs).The simulation results showed that the optimized PDN met the target impedance requirements,achieving a 15%reduction in the number of capacitors utilized,along with lowered cost,enhanced power integrity,and improved reliability of PCBs.