基于FPGA并行实现SVM训练的可重构计算系统

Reconfigurable Computing System for Parallel Implementation of SVM Training Based on FPGA

针对支持向量机在处理大规模数据集时所面临的计算复杂度高和训练时间长的问题,设计了一种基于FPGA并行实现支持向量机训练的可重构计算系统,并分析了不同量化方式下的硬件资源消耗与加速性能。通过采用随机梯度下降法训练支持向量机,使得需要求解的维度与样本的维度相关联,相较于传统的基于二次规划的求解方法可以显著降低计算复杂性。同时,利用基于FPGA的可重构硬件平台设计了专用并行计算结构以加速支持向量机的训练过程。对设计的完整系统进行了软硬件联合仿真,在4个公共数据集上的仿真结果表明,整体模型预测准确率达到90%以上;在训练阶段,相较于采用相同算法的软件实现,所提出的浮点数表示下硬件实现的单个样本处理时间至少减少了2个数量级;定点数表示下硬件实现的单个样本处理时间最大减小了3个数量级;与基于二次规划问题求解的硬件实现相比,单个样本处理速度最快提升了394倍。

To address the problems of high computational complexity and long training time faced by support vector machines when dealing with large-scale datasets,a reconfigurable computing system for parallel SVM training based on FPGA is designed.The hardware resource consumption and acceleration performance under different quantization methods are analyzed.By utilizing the stochastic gradient descent method for SVM training,the dimensions to be solved are associated with the sample dimensions,significantly reducing computational complexity compared to traditional quadratic programming-based methods.Additionally,a specialized parallel computing structure is designed using FPGA-based reconfigurable hardware platform to accelerate the SVM training process.The entire system is jointly simulated in software and hardware.Simulation results on four public datasets show that the overall model prediction accuracy exceeds 90%.During the training phase,compared to software implementation using the same algorithm,the proposed hardware implementation reduces the processing time for a single sample by at least two orders of magnitude under floating-point representation.Under fixed-point representation,the processing time for a single sample is reduced by up to three orders of magnitude.Compared to the hardware implementation based on quadratic programming problem solving,the processing speed for a single sample is improved by up to 394 times.