数字音频传输中的低抖动锁相环设计

Design of Low Jitter Phase-locked Loop in Digital Audio Transmission

阐述采用国内0.18μm工艺,设计并实现一个低抖动锁相环。提出一种三阶低通采样滤波器结构对相位噪声进行优化。锁相环功耗在锁定状态下为60mW,输出时钟频率44.1kHz,抖动为5ps,10kHz频偏下相位噪声为97.61dB/Hz。

This paper describes domestic 0.18μm technology to design and implement a low jitter phase-locked loop,and proposes a structure of a third-order low-pass sampling filter to optimize phase noise.The power consumption of the phase-locked loop is 60mW in the locked state,and the phase noise is 97.61dB/Hz under a frequency offset of 10kHz.