基于动态自重构结构的3D-HEVC帧内预测算法并行化实现

Parallel implementation of a 3D-HEVC intra prediction algorithm based on dynamic self-reconfiguration structure

3D高效视频编码3D-HEVC中帧内预测算法在专用硬件上的实现具有一定的局限性,无法满足帧内预测算法多种模式灵活自主切换的需求,导致编码性能差,硬件资源利用率不高。针对这一问题,提出一种新的3D-HEVC帧内预测算法在可编程动态自重构阵列处理器上的实现方法,该方法基于动态自重构机制,通过可编程控制器实时收集阵列执行状态,监测到阵列对当前任务执行结束后自主下发新的执行任务。通过对不同预测模式映射方案的硬件自主重构,实现算法的灵活切换。实验结果表明,与相关工作相比,该方法在提高灵活性的同时,硬件资源减少了49.1%,计算延迟减少了29.2%。将测试序列经过整个帧内环路测试,测试结果显示,图像质量良好。

The implementation of intra prediction algorithms in 3D high efficiency video coding(3D-HEVC)on dedicated hardware has certain limitations,which can not fulfill the need for flexible and autonomous switching among multiple modes of the intra prediction algorithm.This leads to poor encoding performance and low utilization of hardware resources.To address this issue,a novel implementation method of 3D-HEVC intra prediction algorithm on a programmable dynamically self-reconfigurable array processor is proposed.This method,based on the dynamic self-reconfiguration mechanism,utilizes a programmable controller to collect the execution states of the array in real-time and autonomously issue new tasks once the current task is completed.By achieving hardware-level autonomous reconfiguration for different prediction mode mapping schemes,the algorithm can switch flexibly.Compared with related work,experimental results show that while enhancing flexibility,the hardware resources are reduced by 49%,and the computational latency is decreased by 29.2%.When the test sequences are subjected to the entire intra-frame loop test,the results demonstrate good image quality.