一种改进型4H-SiC超结UMOS器件

Improved 4H-SiC Superjunction UMOS Device

介绍了1种改进型4H-SiC超结UMOS器件。该结构引入上下掺杂浓度不同的P柱并采用底部厚氧化层。P柱可以与N漂移层形成超结结构,从而在保持高击穿电压的同时减小比导通电阻,底部厚栅氧化层可以减小栅漏电容。结合实际的MOSFET工艺,通过SRIM仿真给出了离子注入条件,并通过TCAD软件对器件结构参数进行优化仿真,得到了击穿电压为1035 V、比导通电阻为0.886 mΩ·cm^(2)的超结UMOS器件。

An improved 4H-SiC superjunction UMOS device is introduced,in which splitting P-pillars and thick bottom oxide are adopted.The P-pillars can form a superjunction structure with an N-drift layer,which reduces the specific on-resistance while maintaining a high breakdown voltage.Thickening the bottom oxide will reduce the gate-drain capacitance.Combined with the actual MOSFET fabrication process,the ion implantation condition is given through SRIM simulations,and the device parameters are optimized through TCAD simulations.Finally,a superjunction UMOS device with a breakdown voltage of 1035 V and a specific on-resistance of 0.886 mΩ·cm^(2) is obtained.