基于分裂基FFT的S波段雷达信号处理单元设计与实现

Design and implementation of S-Band radar signal processing unit based on split-radix FFT

回波信号的信息解调主要依赖于FFT完成,本文提出了一种基于分裂基FFT的FPGA实现信号处理单元方案,用于高效解调回波信号信息。在原方案中,距离维解调由DSP完成,速度维解调在PC端进行,但其采用的单核DSP无法同时处理距离维解调与数据上传,导致实时性较低。本文利用FPGA并行处理和灵活可编程的特点,将两次信号解调集成至FPGA中实现,并完成了数据处理与上传的并行设计,提高了数据处理的实时性与可靠性。其中分裂基FFT是实现上述功能的关键,本文通过设计自适应计算单元与数据流控制单元,提升了分裂基FFT的处理速度,相比传统结构,本文方案节省了5.4%以上的计算周期;相比改进后的分裂基FFT,可节省2.31%以上的计算周期。闭环测试结果表明,本文设计的集成化信号处理单元解调得到的目标点信噪比高达70 dB,能够很好地满足信号处理的要求。

The demodulation of echo signal information primarily relies on the FFT.This paper proposes an FPGA-based signal processing unit scheme utilizing the split-radix FFT for efficient information demodulation of echo signal.In the original scheme,range dimension demodulation was performed by a DSP,while velocity dimension demodulation was conducted on a PC.However,the single-core DSP could not handle range dimension demodulation and data uploading in parallel,resulting in suboptimal real-time signal processing.Leveraging the large-scale parallel processing and flexible programmability of FPGA,this paper integrates both demodulations into the FPGA,achieving a parallel design for data processing and uploading,thereby enhancing real-time data processing.The split-radix FFT is crucial for achieving this functionality.By designing adaptive computation units and data flow control units,this paper improves the processing speed of the split-radix FFT.Compared to traditional structures,the proposed scheme reduces computation cycles by over 5.4%;compared to the improved split-radix FFT,it reduces computation cycles by over 2.31%.Closed-loop test results demonstrate that the integrated signal processing unit designed in this paper achieves a target signal-to-noise ratio(SNR)of 70 dB,effectively meeting the requirements for signal processing.