摘要
时空图卷积网络(STGCN)通过图卷积和时间卷积捕获交通数据的空间依赖性和时间依赖性,可有效提升交通速度预测的精度。但是硬件实现交通速度预测STGCN具有计算量大难以满足实际应用的实时性要求、资源消耗大导致成本增高等问题,在优化交通速度预测STGCN模型基础上,提出了一种交通速度预测STGCN的FPGA实现结构组合优化的方法。首先,通过轻量化裁剪和预测数据位宽的精确选择,对交通速度预测STGCN进行了模型优化,以降低计算复杂度和资源消耗,并经过Python仿真验证其可行性。其次,通过采用流水线、并行计算和数据交替流水存取等组合优化策略,提出了一种交通速度预测STGCN的FPGA实现结构组合优化的方法,以提升系统计算速度。最后,使用Verilog编程对交通速度预测STGCN进行了FPGA的实现仿真和硬件测试。利用PeMSD7(M)数据集进行实验,结果显示FPGA实现单数据交通速度预测的时间为355.5μs,相比CPU、GPU平台及FPGA设计方案1对比,其处理速度最大分别提高了25.9倍、6.7倍和3.5倍,证明了交通速度预测STGCN的FPGA实现结构组合优化方法,在保持预测准确性的前提下可较大幅度的提升系统处理速度。
Spatio-temporal graph convolutional network(STGCN)enhances the accuracy of traffic speed prediction by capturing the spatial dependencies and temporal dependencies in traffic data through graph convolution and time convolution.However,the hardware implementation of traffic speed prediction using STGCN faces challenges such as high computational demands that do not meet the real-time requirements of practical applications and high resource consumption leading to increased costs.To optimize the traffic speed prediction STGCN model,a method for optimizing the FPGA implementation structure combination of traffic speed prediction STGCN is proposed.Initially,the model is optimized through lightweight pruning and precise selection of prediction data bit-width to reduce computational complexity and resource consumption,verified by Python simulation for feasibility.Subsequently,an optimization strategy using pipeline,parallel computing,and alternating data stream storage is introduced to enhance system computational speed.Finally,the traffic speed prediction STGCN is implemented and tested on FPGA using Verilog programming.Experiments with the PeMSD7(M)dataset show that the FPGA implementation reduces the time for single data traffic speed prediction to 355.5μs,maximum processing speed increases of 25.9×,6.7×and 3.5×compared to CPU,GPU platform and FPGA design option 1 comparisons,respectively,proving that the proposed method significantly improves processing speed while maintaining prediction accuracy.
作者
谭会生
杨威
严舒琪
Tan Huisheng;Yang Wei;Yan Shuqi(College of Railway Transportation,Hunan University of Technology,Zhuzhou 412000,China)
出处
《电子测量技术》
北大核心
2024年第18期108-119,共12页
Electronic Measurement Technology
基金
湖南省教育厅科学研究重点项目(20A163)
湖南省学位与研究生教学改革研究项目(2022JGYB183)资助。
关键词
交通速度预测
时空图卷积网络
FPGA
硬件实现结构
流水线
并行结构
traffic speed prediction
spatio-temporal graph convolutional network
FPGA
hardware implementation structure
pipeline
parallel structure