一种高PSRR低温漂无运放带隙基准

A high⁃PSRR and low⁃temperature drifting op⁃amp⁃free bandgap reference

针对无运放带隙基准电压源温度特性及电源抑制比差的问题,设计一种高电源抑制比、低温漂的无运放带隙基准电路。该电路通过电流镜进行钳位,避免运算放大器失调电压对输出基准的影响,利用晶体管栅极与三极管基极生成稳定的补偿电流,以降低基准电压的高阶温度系数,输出端采用共源共栅结构提高电源抑制比。基于SMIC 0.18μm BCD工艺在Cadence环境下对电路进行仿真,仿真结果表明:在-40~125℃范围内,电路的温度系数为3.187×10^(-6)/℃,10 Hz时电源抑制比为-88.6 dB,1 MHz时电源抑制比为-50.2 dB。在考虑启动电路影响的情况下,电路在5 V电源下的静态电流为3.78μA,带隙基准的版图面积为160μm×183μm。可实现对基准电压高阶温度项的补偿,降低温度系数,并在没有滤波电容的条件下提高带隙基准的PSRR。

A high power supply rejection ratio(PSRR)and low⁃temperature drifting op⁃amp⁃free bandgap reference voltage source circuit is designed to improve the temperature characteristics and PSRR of the op⁃amp⁃free bandgap reference voltage sources.In this circuit,a current mirror is utilized to clamp the output voltage,thereby mitigating the impact of the operational amplifier's offset voltage on the output reference.A stable compensation current is generated by leveraging the transistor's gate and the triode's base,effectively reducing the high⁃order temperature coefficient of the reference voltage.In the output terminal,a common source common gate structure is employed to enhance the PSRR.The circuits is simulated in the Cadence environment based on the SMIC 0.18μm BCD process.The simulation results indicate that within the temperature range of-40 to 125℃,the circuit's temperature coefficient is 3.187×10-⁶/℃.The PSRR is-88.6 dB at 10 Hz and-50.2 dB at 1 MHz.Considering the impact of the startup circuit,the quiescent current of the circuit is 3.78μA under a 5 V power supply,and the layout area of the bandgap reference is 160μm×183μm.To sum up,the designed circuit can compensate the high⁃order temperature term of reference voltage,reduce the temperature coefficient,and improve the PSRR of bandgap reference without filter capacitor.