随机梯度追踪算法的硬件架构设计

Hardware Architecture Design of Stochastic Gradient Pursuit Algorithm

压缩感知能够有效降低信号的采样速率,但信号恢复需要大量的复杂计算,这给用于重构的专用电路的面积和功耗带来挑战。以牺牲计算精度和增加计算时长为代价的情况下,随机计算能够大幅度减少算术操作过程中的功耗和硬件成本。这一特性使得随机计算在计算密集型电路设计中得到广泛应用。基于随机计算范式,设计了一种使用简单逻辑门搭建的向量内积计算电路,进一步构建了随机梯度追踪算法的硬件架构。相较于传统的二进制计算电路,该架构在Slices资源的使用上减少了83%。对信号长度为256、稀疏度为8的信号进行重构测试,结果显示其重构信噪比达到了18.99 dB,充分验证了该方案的有效性和灵活性。

Compressed sensing can effectively reduce the sampling rate of signals,but signal recovery requires a large amount of complex calculations,which poses challenges to the area and power consumption of the dedicated circuits used for reconstruction.At the cost of sacrificing computational accuracy and increasing computational time,stochastic computing can significantly reduce power consumption and hardware costs during arithmetic operations.This feature makes stochastic computing widely used in computationally intensive circuit design.Based on the stochastic computing paradigm,a vector inner product computing circuit using simple logic gates was designed,and the hardware architecture of the stochastic gradient pursuit algorithm was further constructed.Compared to traditional binary computing circuits,this architecture reduces the use of Slices resources by 83%.A reconstruction test was conducted on a signal with a length of 256 and a sparsity of 8,and the results showed that the reconstructed signal-to-noise ratio reached 18.99 dB,fully verifying the effectiveness and flexibility of the proposed scheme.