一种高速变采样系统输入延时自适应校准方法

A self⁃adaptive calibration method of input delay for high⁃speed sampling system of variable frequency

针对高速采样系统不同采样频率下会产生不同的数据输入延时,提出了一种高速变采样系统输入延时自适应校准方法,该方法以现场可编程门阵列(FPGA)、高速模数转换器(ADC)和时钟芯片为平台设计核心,采用了高速ADC、时钟芯片与FPGA串行外围接口设计、采样频率动态设计、两级降速架构设计、主从时延校准算法等,实现了采样频率动态控制、并行采样支路数量可调和高速采样数据输入延时的动态校准,完成了高速ADC复杂调制信号无误采样的技术工程实践。

Different data input delays will be generated for high-speed sampling systems at different sampling frequencies,a self-adaptive calibration method of input delay for high-speed sampling system of variable frequency is provided.The solution uses FPGA,high-speed ADC and clock chip as the core framework.Serial peripheral interface design between high-speed ADC,clock chip and FPGA,dynamic design of sampling frequency,design of two-stage speed down,master-slave input delay calibration algorithm and so on are adopted.It realized the dynamic control of sampling frequency,the adjustable number of parallel sampling branches and the dynamic calibration of high-speed sampling data input delay.It completed the technical engineering practice of error free sampling with high-speed ADC to sample complex modulated-signals.