完全可编程阀门阵列生物芯片下容错导向的高阶综合算法

Fault-tolerance-oriented High-level Synthesis Algorithm for Fully Programmable Valve Array Biochips

作为新一代流式微流控生物芯片,完全可编程阀门阵列(FPVA)生物芯片具有更高的灵活性和可编程性,已经成为一种流行的生物化学实验平台。然而,由于环境或人为因素,制造过程中通常存在一些物理故障,如通道阻塞和泄漏,这无疑会影响生化检测的结果。此外,高阶综合作为架构综合的首要阶段,其结果的质量直接影响着后续设计的优劣。因此,该文首次研究了FPVA生物芯片高阶综合过程中的容错问题,提出了单元功能转换方法、双向冗余方法、故障映射方法等动态容错技术,为实现高效的容错设计提供了技术保障。通过将这些技术集成到高阶综合设计中,进一步实现了一种高质量的FPVA生物芯片下容错导向的高阶综合算法,包括故障感知的实时绑定策略和故障感知的优先级调度策略,为实现芯片架构的鲁棒性和检测结果的准确性奠定了良好的基础。实验结果显示,所提算法能够得到一个FPVA生物芯片下高质量且容错的高阶综合方案,为后续实现容错物理设计方案提供了有力保障。

As a new generation of flow-based microfluidics,Fully Programmable Valve Array(FPVA)biochips have become a popular biochemical experimental platform that provide higher flexibility and programmability.Due to environmental and human factors,however,there are usually some physical faults in the manufacturing process such as channel blockage and leakage,which,undoubtedly,can affect the results of bioassays.In addition,as the primary stage of architecture synthesis,high-level synthesis directly affects the quality of subsequent design.The fault tolerance problem in the high-level synthesis stage of FPVA biochips is focused on for the first time in this paper,and dynamic fault-tolerant techniques,including a cell function conversion method,a bidirectional redundancy scheme,and a fault mapping method,are presented,providing technical guarantee for realizing efficient fault-tolerant design.By integrating these techniques into the high-level synthesis stage,a high-quality fault-tolerance-oriented high-level synthesis algorithm for FPVA biochips is further realized in this paper,including a fault-aware real-time binding strategy and a fault-aware priority scheduling strategy,which lays a good foundation for the robustness of chip architecture and the correctness of assay outcomes.Experimental results confirm that a high-quality and fault-tolerant high-level synthesis scheme of FPVA biochips can be obtained by the proposed algorithm,providing a strong guarantee for the subsequent realization of a fault-tolerant physical design scheme.