面向异构加速卡的MF-DMA设计与实现

Design and implementation of MF-DMA for heterogeneous accelerators

为解决加速卡在异构系统中数据传输带宽低、数据交互方式不灵活的问题,提出一种多功能直接内存访问(multiple functions direct memory access,MF-DMA)架构。采用寄存器配置、存储表和描述符环3种DMA触发方式,适应不同应用数据传输需求;为支持数据流传输和数据块缓存,DMA架构支持AXIS和AXI4两种标准协议接口;设计在Xilinx芯片xczu7ev进行验证,AXIS和AXI4接口最高速率分别为5075 MB/s和4800 MB/s,PCIe总线带宽利用率为79.2%,FPGA资源占用率12.9%。实验结果表明,该设计降低了硬件资源占用率,有效提高了数据传输性能。

Aiming to enhance the data transmission bandwidth and the flexibility of data exchange methods in heterogeneous acceleration systems,a design scheme called multiple functions direct memory access(MF-DMA)architecture was proposed.Three DMA triggering methods including register configuration,RAM list,and descriptor ring,were introduced to accommodate various application data transmission requirements.The MF-DMA data transmission port supported AXIS and AXI4 protocol interfaces,enabling streaming data transmission and block data memory cache support.The effectiveness of the proposed scheme was verified through experiments conducted on the Xilinx chip xczu7ev.The maximum speed achieved for AXIS is 5075 MB/s,for AXI4,it is 4800 MB/s.The utilization of the PCIE bus bandwidth reaches 79.2%,while the FPGA resource utilization rate is only 12.9%.Experimental results confirm that the proposed design significantly improves data transmission performance and effectively reduces resource utilization.