刷新模式可选的高分辨率数字驱动LCoS芯片设计

High-Resolution Digital LCoS Chip Design with Selectable Refresh Mode

提出了一种高分辨率数字驱动LCoS芯片的设计方案,可用作全光通信网中核心的波长选择开关。给出了LCoS芯片驱动算法、总体架构及组成模块设计仿真和系统验证测试结果。像素单元采用了9T静态随机存取存储器(SRAM)方案,同时在数字驱动像素上实现高速逐行刷新和全局刷新两种可选模式。本设计基于0.18μm互补金属氧化物半导体(CMOS)工艺,通过优化得到了5.5μm×3.5μm的相对较小像素尺寸,并实现了10 bit灰度等级、3840×2160的阵列规模和60 Hz帧频。经过现场可编程门阵列(FPGA)系统性测试和像素单元后期仿真,验证了本方案能有效满足设计要求。

This paper presents a design scheme of high-resolution digital LCoS chip,which can be used in the wavelength selective switch in all-optical communication networks.The LCoS chip-driving algorithm,overall architecture,component module simulation,and system verification results are presented.The pixel unit adopts the 9T static randomaccess memory(SRAM)scheme,which realizes two selectable modes of high-speed progressive refresh and global refresh on digital pixels for the first time.This design is based on 0.18μm complementary metal-oxide-semiconductor transistor(CMOS)technology.Through optimization,the relatively small pixel size of 5.5μm×3.5μm is achieved.A 10 bit gray scale,3840×2160 resolution,and 60 Hz frame rate are realized.Systematic verification via field-programmable gate array(FPGA)and post-simulation of the pixel unit verify that the proposed scheme satisfies the design requirements.