基于FPGA的LVDS转以太网接口的测试工装

Testing equipment of LVDS to Ethernet interface based on FPGA

在应用风洞试验对某结构模型进行动态测试时,需要用数据记录仪对多次试验过程的状态信息进行存储记录以及回读分析。数据记录仪的接口为LVDS接口,为了方便在地面阶段用上位机对记录仪进行指令下发以及回读测试,设计了一款LVDS转以太网的测试工装。此装置采用FPGA作为主控芯片,以8B/10B编解码的方式对LVDS线路的信号进行传输稳定性处理,通过以太网接口与上位机进行通信。记录仪的数据经LVDS传输至FPGA中的RAM,采用双RAM缓存提高传输效率,随后将RAM中的数据封装为以太网UDP/IP帧格式,在UDP协议的基础之上通过双RAM交替缓存实现指令-数据的“握手”操作,并使用CRC校验以及数据重传的方式降低传输过程中的误码率,最后通过物理层芯片发送至上位机。经验证,LVDS+FPGA+以太网的数据传输是可行的,具有良好的稳定性和可靠性,可应用于实际工程。

During the dynamic tests on a structural model using wind tunnel experiments,it is necessary to store,record,and analyze the status information of multiple test processes using a data recorder.The data recorder utilizes an LVDS(Low Voltage Differential Signaling)interface.To facilitate the issuance of commands and playback tests with an upper computer during the ground phase,an LVDS to Ethernet test fixture was designed.This device employs an FPGA(Field-Programmable Gate Array)as the main control chip,utilizing 8B/10B encoding and decoding to ensure the stability of signal transmission over the LVDS line.Communication with the upper computer is achieved through an Ethernet interface.Data from the recorder is transmitted via LVDS to RAM in the FPGA,and dual RAM buffering is used to enhance transmission efficiency.Subsequently,the data in the RAM is encapsulated into Ethernet UDP/IP frame format.On the basis of the UDP protocol,a command-data"handshake"operation is achieved through alternating dual RAM buffers.CRC(Cyclic Redundancy Check)verification and data retransmission methods are used to reduce the error rate during transmission.Finally,the data is sent to the upper computer through a physical layer chip.Validation has shown that data transmission using LVDS,FPGA,and Ethernet is feasible,with good stability and reliability,making it suitable for practical engineering applications.