一种高性能CMOS运算放大器的设计

The Design of a High-Performance CMOS Operational Amplifier

为适应当前芯片趋于高速电路的发展趋势。本文设计了一款具有高宽带、高增益性能的运算放大器电路。它采用了深亚微米CMOS的28nm工艺和IO端口1.8 V电源电压来实现。该电路主要利用了增益自举增强技术结合共源共栅结构来提升放大器的增益。在Cadence环境下完成电路设计和Spectre仿真验证,仿真结果表明:电路的直流增益达到96 dB以上,单位增益带宽为251 MHz,电源电压抑制比为86.7 dB,压摆率为33 V/us(负载电容为1pF),功耗小于0.15 mW,实现了较低的电路功耗。这在高速电路的比较、滤波等应用具有重要的参考价值。

In order to adapt to the current development trend of chips towards high-speed circuits.In this paper,It designs a high-bandwidth,high-gain and high-performance operational amplifier circuit.It uses a 28-nm process of deep sub-micron CMOS and a 1.8V supply voltage of the IO port.This circuit mainly uses gain bootstrap enhancement technology combined with cascode structure to improve the gain of the amplifier.It completes circuit design and Spectre simulation verification in Cadence environment.The simulation results show that the circuit's DC gain reaches more than 96 dB,the unity gain bandwidth is 251 MHz,the supply voltage rejection ratio is 86.7 dB,the slew rate is 33 V/us(the load capacitance is 1pF),and the power consumption is less than 0.15 mW,achieving low circuit power consumption.This has important reference value in high-speed circuit comparison,filtering and other applications.