超深亚微米芯片互连线电感提取技术及应用

Research on inductance extraction for on-chip interconnects in DSM designs

超深亚微米(VDSM)工艺下,集成电路的高频、高集成度趋势使互连线间电磁耦合作用不容忽略.首先回顾了典型电感提取方法及实际应用中电感阵稀疏化、模型降阶等问题;基于互连线分布RLC模型,对一类电源树的同步切换噪声问题作了分析;并介绍了RL梯状电路、有效电容法等实用电感效应处理措施.一些仿真实例表明,未来高频集成电路中电感效应可严重影响部分关键互连线网性能,将成为信号完整性的重要制约因素.

Circuits with increasingly higher speed are being integrated at higher density under very deep sub micron (VDSM) technologies. The strong electromagnetic coupling existing widely among onchip interconnects can no longer be ignored. Some problems that occurred in IC analysis, such as sparsity and stability, model order reduction are first discussed. Research on simultaneous switching noise analysis in power supply trees, concept of RL ladder circuit and effective capacitance are then presented. Some simulation results showed that the inductive effects influence greatly some VLSI key interconnect, and comprise important limitation on the signal integrity.