摘要
提出了一种可综合算术运算单元的性能评估与建模方法 .该方法以单位门面积及延迟模型为基础 ,在设计的早期即可估算电路的面积、延迟等性能指标 ,从而便于设计者进行 VL SI结构的优化 ,避免设计叠代 ;并以算术运算中最典型的二进制加法器为例 ,研究如何利用该模型对电路的 VL SI实现结构进行评估、优化 ;理论分析的结论与电路的实现结果吻合 。
A performance evaluation and modeling method for synthesizable arithmetic circuit is proposed.Based on the unit gate model,it is feasible to estimate the delay and area of arithmetic circuits at the beginning of design period,therefore the design iteration is avoided.The effectiveness is proved by the applications of the proposed method to various binary adders.
