摘要
文章讲述了一种8点FFT的verilogHDL设计实现,着重阐述了有符号的复数加/减法器的设计,并给出了整个系统仿真的结果,该设计可以在4个时钟内计算一个数据。最后该系统在Altera公司的FLEX10K的FPGA上成功地实现了综合,实验结果证明这种设计方法不但具有设计方法简单的优点,而且吞吐量可以达到2M/s的变换速度,已经完全能够满足目前一些系统的要求(如OFDM系统)。
A reasonable logic structure for a8-point FFT processor is described and the simulating result is given in my paper and we expatiate stressly the signed complex adder /subtracter concept.The architecture can compute one transform sample every4clock cycles in average.And the design has been implemented in the FLEX10K family of FPGAs.The throughput is up to2M transform samples per second,and such performance makes the design rather attractive for use in some applications,such as OFDM systems.
出处
《微电子学与计算机》
CSCD
北大核心
2002年第11期5-17,10,共14页
Microelectronics & Computer
基金
国家创新研究群体科学基金项目(60024301)
