相干偏振复用正交相移键控实时相干接收中的并行流水型恒模算法(英文)

Parallel and Pipelined CMA for a Coherent Polarization Multiplexed Quaternary Phase Shift Keying Realtime Coherent Receiver

在对相干偏振复用四相相移键控信号进行偏振解复用的实时相干接收机中,为高效补偿偏振效应,同时降低系统对时钟频率要求与系统中FPGA资源的使用量,对接收机中广泛采用的恒模算法从并行性、滤波器阶数、以及流水性3方面进行了研究改进,提出了并行流水型恒模算法.研究结果显示,在43Gb/s高速相干接收系统中,相干接收机的并行度宜为32,滤波器阶数宜为5.VPI与MATLAB联合仿真结果表明,采用本文提出的并行流水型恒模算法后,基于FPGA的四相相移键控信号实时相干接收机对时钟频率的要求可以降低到168MHz;在不丢包的情况下,系统能够处理43Gb/s相干接收系统中的全部数据,有效实现偏振解复用;在背靠背情况下,补偿1×10-3误码率的OSNR为14.5dB.利用高层次综合软件将并行流水型恒模算法下载到FPGA中,DSP资源的使用量仅仅是传统算法使用量的1/8.

In order to compensate for polarization dependent effects in an FPGA-based coherent polarization multiplexed quaternary phase shift keyingrealtime coherent receiver with a low requirement for clock frequency and FPGA resources,an optimization on conventional constant modulus algorithm was given from aspects of parallelism,tap length of coefficient and pipelining technology.Simulation results show that the proposed parallel and pipelined constant modulus algorithm can reduce requirement for high clock frequency in a FPGA-based realtime coherent receiver effectively.Processing a complete data stream in a 43Gb/s coherent receiver without discarding any data blocks at a clock frequency of 168 MHz was achieved in the simulation.The required OSNR in back-to-back transmission for a BER of 1×10-3 was14.5dB.A high level synthesis software shows that DSP usage is 1/8of that with conventional parallel constant modulus algorithm.