使用改进的心动阵列结构实现RSA公共密钥算法

Implementation of RSA Cryptosystem with Improved Systolic Array Architecture

本文介绍了一种 RSA算法的电路实现结构。该结构是对心动阵列结构的改进 ,对心动阵列结构的核心模块长加法模块进行了循环复用 ,在大幅度降低电路面积的情况下 ,运算速度没有明显的降低。用 Verilog描述了整个设计 ,并在

In this paper, we propose a kind of improved systolic array architecture for the implementation of RSA cryptosystem. In this architecture, we regard the long adder module as the iterative core, and reuse it. Although we reduce the circuit area highly, we don′t slow down the process speed. The design is expressed in Verilog, and is verified by FPGA.