期刊文献+

基于神经网络的MCM互连故障模拟器研究

A Study on MCM Interconnect Fault Simulator Based Upon the Neural Network
下载PDF
导出
摘要 故障模拟器是基于模拟算法的测试生成系统的重要组成部分,其性能优劣直接影响测试集的各项指标。在基本互连结构的二值Hopfield神经网络模型基础上,提出了一种利用神经网络技术实现MCM互连故障模拟的方法。该方法以能量函数值反映故障状态的原理为基础,将判定测试矢量对故障的检测能力问题转化为能量函数值求解问题,简化了故障模拟的处理过程,提高了模拟效率。实验结果表明,用这一方法实现的验证性互连故障模拟器ICFSim,可以有效地对互连网络中的固定型故障和两两短路型故障进行快速模拟。 The fault simulator is an important part of a simulating based automatic test generating system,and its performance greatly affects the quality of the gained test vector set. Based upon the fundamental models of discrete Hopfield neural network for interconnects, a novel fault simulating method for MCM interconnects is put forward. Since the energy function value could reflect the faults status, the complicated decision toward testability of certain vectors is transferred by the method to calculating the corresponding energy function values of the faulty Hopfield neural network models, to make the fault simulation processing simpler and to acquire a better simulating efficiency. The result of the experiment proves the Hopfield neural network based fault simulating method an effective one.
出处 《桂林电子工业学院学报》 2002年第6期1-5,共5页 Journal of Guilin Institute of Electronic Technology
基金 国防科工委跨行业基金项目(J17.1.5DZ0503)
关键词 神经网络 MCM 多芯片组件 互连故障 故障模拟 能量函数 高密互连 MCM(Multi-chip Module), neural network, interconnect faults, fault simulation, energy function
  • 相关文献

参考文献6

  • 1IEEE Standard 1149.1-1990,IEEE standard test access port and boundary scan architecture[S].
  • 2Kautz W K.Testing of faults in wiring interconnects[J].IEEE Transactions on Computer,1974,C-23(4):358-363.
  • 3Goel P and McMahon M T.Electronic chip-in-place test[C].Proceedings of IEEE International Test Conference,1982.83-90.
  • 4Wagner P T.Interconnect testing with boundary scan[C].Proceedings of IEEE International Test Conference,1987.52-57.
  • 5卢静,周娅,郭学仁.基于遗传算法的PCB互连测试矢量集优化初探[J].桂林电子工业学院学报,2000,20(3):41-44. 被引量:2
  • 6Hopfield J J.Neurons with graded response have collective computational properties like those of two-state neurons[J].Proceedings of National Academy of Sciences,1984,81:3088-3092.

二级参考文献4

  • 1 Saab D G,andAbraham J.CRIS:A test cultivstion porgram for sequential VLSI circuits[J].IEEEInt.Conf.On Computer-Aided Design,1992:216-219
  • 2 Saab D G,Saab Y G and Abrham J.Automatic test vector culitivation for sequentialVLSI circuits using genetic algoritms[J]. IEEE Trans.on Computer-Aided Design,1996,15(10):1278-1285
  • 3 沈理.时序电路的时序深度分析及基于遗传算法的初始化[A].CETC-8论文集[C],1999:61-67
  • 4 Pomeranz I and Reddy S M.On Improving Genetic Optimization based TestGeneration.in Proc.Europ[J].Design & Test Conf,1997,(5):506-511

共引文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部