VXI总线从模块时序控制器的VHDL语言设计

Design of a sequence-controller in a VXIbus slave-module in VHDL

介绍了VXI总线从模块时序控制器的动作过程及其特点 ,并基于VHDL硬件描述语言 ,用异步MEALY状态机的方法进行VXI总线寄存器基接口的时序控制器的设计。

This paper introduces the action's process and character of a sequence controller in a VXIbus slave module, and how to design the sequence controller using asynchronous MEALY state-machine in VHDL language.