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递归学习寻找对称变量 被引量:1

Recognizing Symmetric Variables Using Recursive Learning
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摘要 逻辑验证和逻辑综合中 ,利用对称变量的性质能提高算法整体的效率 .通常 fxixj=fxjxi被用来检验变量的对称性 .一般先分别建立 fxixj和 fxjxi的 BDD( Binary Decision Diagram)二分决策图 ,然后通过检查两 BDD图是否同构来验证 fxixj=fxjxi.但将电路转化为 BDD图本身就需要一定的时间 ,而且对于大的电路 ,存在 BDD图不能建立的可能性 ,致使同构验证无法进行 .本文利用递归学习 ,无需建立 BDD图直接在电路拓扑图上验证 fxixj=fxjxi.递归学习算法执行效率高 ,可以大大缩减对称变量检测的过程 .试验结果表明 ,利用递归学习算法检测对称变量执行时间减少 ,并且能将大的电路作为检测对象 . In logic synthesis and verification, information of symmetry variables can improve algorithms' efficiency. As usual, f x i j =f x j i is used to detect the symmetry variables. After building two BDDs (Binary Decision Diagrams) according to f x i j and f x j i ,one can say these two variables are symmetry if the two BDDs are isomorphic. But BDD is sensitive to the order of variables and sometimes it can not be built because of its enormously big size. In this paper, recursive learning is used to detect symmetry variables without building BDD. Recursive learning runs with high efficiency, which is helpful to reduce the detecting time. The results show that the recursive learning can run in less time and deal with big circuits where BDD can not be built.
出处 《上海交通大学学报》 EI CAS CSCD 北大核心 2002年第12期1709-1712,共4页 Journal of Shanghai Jiaotong University
基金 美国国家科学基金资助项目 (5 978East Asia andPacific Program-960 2 485 )
关键词 逻辑集成电路 对称变量 递归学习算法 测试生成 逻辑函数 二分决策图 logic integrated circuits symmetry variables recursive learning test generation
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参考文献6

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同被引文献9

  • 1李光辉,邵明,李晓维.通用CPU设计验证中的等价性检验方法[J].计算机辅助设计与图形学学报,2005,17(2):230-235. 被引量:4
  • 2李晓维 吕涛 李光辉.集成电路设计验证[J].中国科学院计算技术研究所内部刊物-信息技术快报,2004,(9).
  • 3Dr.Eng.Ka Lok Man.Efficient Equivalence Checking of Industrial Designs[C].In Proc.of IEEE Design Verification Conference in Europe.2001:1-10.
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  • 6H.Fujiwara,T.Shimono.On the acceleration of test generation algorithms[J].IEEE Trans.on Computers,1983,32(12):1137-1144.
  • 7M.Schulz,E.Frischler,T M.Sarfert.SOCRATES:A highly efficient automatic test pattern generation system[J].IEEE Transaction on Computer-Aided Design,1987,7(1):126-137.
  • 8Y.Matsunaga.An Efficient Equivalence Checker for Combinational Circuits[C].In 33rd Design Automation Conference,1996:629-634.
  • 9李光辉,邵明,李晓维.基于BDD的组合电路等价性检验方法[J].微电子学与计算机,2003,20(2):48-51. 被引量:4

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