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一种基于FPGA的数字信道化工程实现

AN Engineering Realization of Digital Channelized Based on FPGA
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摘要 传统的数字信道化在信道划分时存在盲区,落入盲区信号的检测概率会随之降低,同时还有可能产生虚假信号。在现有的宽带数字信道化接收机结构的成熟理论基础上,设计一种50%重叠的滤波器组,同时将过采样率提高一倍,消除相邻信道之间的盲区,每个信道的数据率也提高了一倍,很好地解决了相邻信道混叠问题。这种方法可以实现跨通道信号的最优信道判决,避免产生虚假信号,可以对信号进行全概率截获。最后使用MATLAB进行了仿真和验证,并在FPGA上实现。 Blind zone will be generated in traditional digital channelization. When the signal appear in the blind zone, maybe a false signal will be generated and the detectable rate can be reduced. Based on mature theory of existing wide band digital channelized structure, a 50% overlap polyphase filter banks was designed.AT the same time, the over sampling rate increase of 100%.It will avoid the blind zone, and the data rate in each channel will be increased. Then, the problem of neighborhood channel overlap is solved. This method can adjudge the best channel of cross-channel signal to avoid the false signal generation. The signal can be interecepted total probability. The simulation testing and verification were performed with Matlab,and then realize on FPGA.
作者 陈威 刘鑫超
出处 《信息通信》 2016年第6期10-12,共3页 Information & Communications
关键词 数字信道化 信道划分 多相滤波器组 FPGA digital channelized channel partition Polyphase Filter Banks FPGA
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