采样时钟抖动、相噪与输出SNR关系研究

Research on Clock Jitter、Phase Noise and Output SNR Relationship

射频数字化技术是软件无线电接收机理想实现形式,并随着高速、高分辨ADC技术的飞速发展在雷达、通信、电子战领域得到了广泛的应用。由于采样时钟对射频信号的卷积效应和采样折叠效应,采样时钟的性能将直接决定输出信号的SNR。文章对射频数字化采样时钟抖动、相位噪声与输出SNR关系进行了研究、仿真和试验,给出了不同应用场合和需求下时钟对抖动、相位噪声的要求,可用于指导射频数字化采样时钟的设计。

RF digitalization is the ideal implemented style of software defined radio, and widely used in radar、communication and electronic warfare with the rapidly development of high-speed、high-resolution ADC technology. Because of convolution and folding effect of sampling clock on RF signal, sampling clock performance directly determine the ADC output SNR. Research、simulation and test of RF sampling clock jitter、phase-noise and output SNR relationship were discussed in this paper,clock jitter and phase noise requirement of different application and performance demand also given, which used for RF digitalization sampling clock signal deign.