星载计算机存储器的滞后检错纠错方法

A Delayed Error Detection and Correction Method for SRAM

本文针对在使用新型商用处理器构建航天器容错计算机系统的过程中 ,商用处理器的高速处理能力要求与存储器检错纠错对速度的影响之间的矛盾 ,提出了一种新的存储器校验方式———滞后校验来解决这个矛盾 ,并尝试把这种校验方式和具有多位纠错能力的RS (Reed -Solomon)编码结合起来完成存储器的校验 ,最后本文探讨了这种校验方式所带来的问题 。

This thesis presents the construction of the fault-tolerant computer on spacecrafts. It is focused on a new correction-after-execution method of memory error detection and correction (EDAC), and is intended to solve the conflict between the high speed demand of commercial CPUs and the negative influence on speed by EDAC for memory. The memory correction method is based on Reed Solomon (RS) code correcting the multi-bit single event upset (SEU) errors. The problem resulted from the method will be discussed and the idea of solution will be brought up.