FPGA焊点连接失效故障诊断

Research on the fault diagnosis technology of connection failure belonging to the FPGA solder joint

利用焊点内建自测(solder joint built-in self-test,SJ BIST)方法,建立球栅阵列(ball grid array,BGA)封装现场可编程门阵列(field programmable gate array,FPGA)焊点连接失效故障诊断的模型,用multisim进行仿真,并在Altera DE2平台上进行验证.结果表明,相比已有的文献资料,文中对SJ BIST诊断方法进行了更详细论证,更详细地确定了焊点阻抗大小,从而可得到更准确的FPGA焊点健康状态信息.

This paper presents a model for detecting faults in FPGA( field programmable gate array) devices of BGA( ball grid array) type of packages using the method of SJ BIST( solder joint built-in self-test). It was theoretical analyzed in details,and simulated by simulation software- multisim. The DE2 hardware system of the Altera corporation was used to verify the model. The results showed that,compared with reference,the method of SJ BIST was analyzed in more detail,and the accurate impedance could be determined more accurately,and more exact information about health state of the FPGA solder joints can be obtained.