1[1]Dr. Roland E Best.Phase-Locked loops: Theory, Design, and Appli-cations [M].New York:McGraw-Hill,1984
2[2]William C Lindsey, Chak Ming Chie.A survey of digital phase-locked loops [J].Proceedings of the IEEE,1981,69(4):410-431.
3[3]Stephen M Walters, Terry Troudet.Digital phase-locked loop with jitter bounded[J].IEEE Transactions on Circuits and Systems,1989,36(7):980~986
4[4]Shayan Y R, Le-Ngoc T.All digital phase-locked loop: concepts, design and applications [J].IEE Proceedings,1989,136(1):53-56.
5[5]Fumiyo Sato,Takahiko Saba,Duk-Kyu Park,et al.Digital phase-locked loop with wide lock-in range using fractional divider[C].IEEE Pacific Rim Conference on Communications, Computers and Signal Processing,1993,2:431-434.
6潘松 黄继业 王国栋.现代DSP技术[M].西安电子科技大学出版社,2003年8月..
7Dr Best Roland E. Phase-Locked loops: Theory, Dsign and Applications[M]. New York: Mcgraw-Hill, 1984.
8王福昌 鲁昆生.锁相技术[M].武汉:华中科技大学,2002..
9Lindsey William C, Chie Chak Ming. A survey of digital phase-locked loops[J]. Proceedings of the IEEE, 1981, 69(4): 410-431.
10Walters Stephen M, Troudet Terry. Digital phase-locked loop with jitter bounded[J]. IEEE Transactions on Circuits and Systems, 1989, 36(7): 980-986.