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主从型D触发器的动态功耗分析 被引量：2

Dynamic power analysis of master-slave D flip-flop.
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摘要 主从型D触发器的动态功耗同触发器内部节点上的信号跃迁情况和节点电容有关.基于D触发器的电路结构与MOS管参数,本文对主从型D触发器各个节点电容进行了计算.利用对各节点电容的计算值,便可估算在某一激励输入序列下的D触发器的动态功耗.Pspice模拟证实了该一动态功耗估算的准确性.搞清了D触发器内部诸结点电容与MOS管参数之间的关系亦为降低它的动态功耗提供了参考依据. The dynamic power dissipation of a master-slave D flip-flop (MSDFF) depends on the signal transitions and capacitances of the nodes inside the MSDFF. Based on the circuit configuration of the D flip-flop and parameters of MOS transistors, the capacitances of the nodes inside the D flip-flop are calculated in this paper. With these caluculated capacitances, the dynamic power of a MSDFF can be estimated for a given excitation input sequence. The precision of the estimation is verified by Pspice simulation. The relationship between node capacitances inside the D flip-flop and parameters of MOS transistors offers reference for reducing its dynamic power dissipation.
作者 王伦耀 吴训威
机构地区 宁波大学电路与系统研究所 浙江大学信息与电子工程学系
出处 《浙江大学学报（理学版）》 CAS CSCD 2003年第1期35-40,共6页 Journal of Zhejiang University（Science Edition）
基金 国家自然科学基金资助项目(60273093) 浙江省科技厅资助项目(0601110022)
关键词 动态功耗 功耗估计 主从型D触发器 CMOS集成电路 节点电容 电路结构 dynamic power power estimation master-slave D flip-flop
分类号 TN432 [电子电信—微电子学与固体电子学] TN783 [电子电信—电路与系统]
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参考文献11

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同被引文献9

  • 1Telllez G E, Farrah A, Sarrafzadeh M. Activity-driven clock design for low power circuits. Proc. IEEE ICCD, TX, USA, 1995,11: 62- 65.
  • 2Wu X (吴训威), Wei J (韦健). CMOS edge-triggered flip-flop using one latch. Electron. Lett., 1998, 34 (16): 1581 - 1582.
  • 3Wu X (吴训威). Theory of transmission switches and its application to design of CMOS digital circuits. International Journal of Circuit Theory and Application, 1992, 20(4):349 - 356.
  • 4Rabaey J M. Digital Integrated Circuits: A Design Perspective.New York: Prentice-Hall Inc. 1996:60 - 62.
  • 5Tellez G E, Farrah A, et al. Activity-driven clock design for low power circuits [A]. Proc. IEEE ICCAD [C]. 1995-11: 62-65.
  • 6Manolescu M, Lin I-Pei. Low-power half-static flip-flop structure [A]. Proc.Int. Semicond. Conf. [C]. 2000-10: 211-214.
  • 7Wu X (吴训威), Wei J (韦健). CMOS edge-triggered flip-flop using one latch [J]. Elect. Lett., 1998, 34(16): 1581-1582.
  • 8Strollo A G, Napoli E, Cimino C. Low power double edge-triggered flip-flop using one latch [J]. Elect. Lett., 1999, 35(3): 187-188.
  • 9Qiu X, Chen H. Discussion on the low-power latches and flip-flops [A]. Proc. Int. Conf. on Solid-State & Integrated Circuit Tech. [C]. 1998-09: 477-478.

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浙江大学学报（理学版）
2003年 第1期

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