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用于高速运算单元的时钟延迟动态多米诺逻辑电路的设计

Design of Clock-Delayed Domino Logic for High Speed Arithmetic Unit
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摘要 时钟延迟多米诺逻辑是一种自定时的动态逻辑。时钟延迟多米诺逻辑门的输出信号是单向跳变的,但它可以提供倒相和非倒相的输出。使用这种动态逻辑可以大大提高运算电路的速度。本文通过一个64位的快速并行加法器的实现说明时钟延迟多米诺的特性及其设计方法。这个快速并行加法器用于高性能的64位微处理器的运算单元中。采用O.25μmCMOS工艺设计了这个加法器。加法器在最坏情况下的运算时间是700ps。这个时钟延迟多米诺加法器比使用相同单元库和技术的静态逻辑加法器快2.3倍。 Clock-delayed domino is a self -timed dynamic logic developed to provide single - rail gates with inverting or noninverting outputs. The speed of arithmetic circuits can be improved dramatically by using this kind of dynamic logic. A 64bit high - speed parallel adder is designed to show the characteristic and the design method of Clock -Delayed domino logic, using 0. 25μm CMOS process technology. The parallel high - speed adder was designed for the arithmetic unit in the high performance 64bit microprocessor. The addition time is 700ps in the worst condition. The Clock-Delayed domino adder is 2. 2×faster than static logic adder with the same cell library and technology.
出处 《微处理机》 2002年第4期14-16,20,共4页 Microprocessors
关键词 时钟 电路 并行加法器 动态多米诺逻辑 自定时电路 高速电路 paralle adder,dynamic domino logic,self-timed circuit
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参考文献5

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