一种位级流水线乘法器的设计

A Design on the Bit-Level Pipelined Multiplier

本文提出一种位级流水线乘法器的设计方法。在算法上考虑了无符号数与符号数各种组态的乘法运算;采用并行的半脉动阵列结构,节省了大量寄存器;使用带寄存的多米诺电路型式,减少了器件数、提高了速度并降低了功耗。按这种方法设计的8×8乘法器所需器件数少于3000个,采用2μmCMOS工艺可以达到100MHz以上的流水线工作频率。

A design method on the bit-level pipelined multiplier is presented in this paper. An algorithm is derived to perform both unsigned and signed multiplication. The parallel semi-systolic array architecture dramatically saves register number, while latched Domino circuitry cuts down the device count, increases speed and lowers power consumption. A 8×8 bit multipler according to this method requires less than 3000 devices and can work at the frequency greater than 100 MHz using 2 μm CMOS technology.