基于混合图的总体布线调整

Mixed Graph Based Global Wiring Refinement

本文提出了一种基于混合图的总体布线调整方法。混合图是对表示布局的有向图进行一系列精确的顶点分解而产生的。用得到的图模型来表示总体布线信息,从而可以在总体布局优化的同时估计布线对芯片面积的影响,并对总体布线进行调整。由于总体布线是自动更新的,所以布局同时随着布线的调整和模块的移动而改进。本文还提出了多种瓶颈的概念和瓶颈间走线随模块旋转而变化的规律。最后给出的实验结果表明,这种算法在减小芯片面积上获得比较好的结果。

A global wiring refinement method based on mixed graph model is presented in this paper. The mixed graph model is the consequence of a series of precise vertex decomposition applied to the digraph representation of a floorplan. The graph model is utilized for new expression of global wiring information. Effects of global wiring on chip area can then be estimated and optimized in the layout refinement stage. Global wiring is automatically revised, so placement is affected and improved by wiring and block arrangement. Satisfactory results were obtained by several runs on practical chips.