摘要
介绍了一个用于高性能的微处理器和 DSP处理器的快速 6 4位二进制并行加法器 .为了提高速度 ,改进了加法器结构 ,该结构大大减少了加法器各级门的延迟时间 .基于改进的加法器结构 ,有效地使用动态复合门、时钟延迟多米诺逻辑和场效应管尺寸缩小技术 ,可以取得良好的电路性能 .该加法器采用 U MC 2 .5 V 0 .2 5μm 1层多晶 5层金属的 CMOS工艺实现 .完成一次加法运算的时间是 70 0 ps,比传统结构的加法器快 2 0 % ;面积和功耗分别是0 .16 m m2和 2 0 0 m W@5 0 0 MHz,与传统结构加法器相当 .
A fast 64bit binary parallel adder for high performance microprocessors and DSP processors is presented.Modified adder architecture is proposed,which reduces the gate delay of each stage in the adder dramatically.Efficiently using of dynamic compound gates,clock delayed domino logic and FET scaling technique,the modified adder architecture achieved good performance.The adder is implemented in UMC 2 5V 0 25μm 1P5M CMOS technology.The addition latency is 700ps,20% faster than that of conventional architecture adder.The area and power dissipation are 0 16mm 2 and 200mW at 500MHz respectively,which is similar to that of conventional architecture adder.
