VHDL语言在个体域D为{0,1}的谓词逻辑定理证明中的应用

Application of VHDL Language in Testifying Predicate_Logic Whose Universe D is{0,1}

提出了以VHDL语言为手段，介绍了针对个体域D为{0,1}的谓词逻辑定理证明的实现方法，并在Active-HDL环境中举例说明。

This paper proposes the application of VHDL language in testifying Predicate_Logic whose universe D is{0,1}, and exemplifies in Active-HDL。