三维VLSI互连寄生电容提取的研究进展

Research Progress on 3-D VLSI Parasitic Capacitance Extraction

随着VLSI电路集成密度急剧增长及特征尺寸不断缩小 ,互连寄生参数提取已成为集成电路辅助设计中的一个研究热点 .目前 ,三维互连寄生电容提取的研究得到广泛关注 ,并取得了很大进展 .针对这一热点 ,结合作者的研究工作 ,对三维电容提取方法进行综述 ,详细阐述国内外的相关研究进展情况 .重点介绍间接、直接边界元方法 ,以及维度缩减技术和区域分解法等半解析方法 .

In the deep submicron VLSI circuits, with the feature size scaled down and device density increased, parasitic parameter extraction has become one of the research focuses in the field of electronic design automation. Main methods and technology of 3 D parasitic capacitance extraction are discussed. Corresponding research progress and important results in this field are also presented.