Verilog RTL模型

Verilog RTL Model

VLSI集成电路芯片测试技术正在向高层次测试推进 .针对Verilog硬件描述语言 ,提出了一种在寄存器传输级 (registertransferlevel,RTL)上的电路模型VRM .该模型着重于实际应用 ,可输出文本格式文件 ,便于开发实用的RTL级故障模拟和RTL级测试生成等软件 .基于该模型 ,还实现了一个简单的RTL逻辑模拟程序以验证VRM模型的可行性 .

The VLSI testing is being pushed to the high-level based technology.The paper presents a Verilog RTL model(VRM) for integrated circuits.It provides a text format file that may be useful for developing RTL fault simulation and test pattern generation tools in practice.Based on the VRM,a simple RTL logic simulator was implemented for verification of the model.