RTL集成电路的时序深度

Sequential Depth of Integrate Circuits Based on Register Transfer Level

在高层次测试生成中 ,为了更好地利用高层次电路的结构信息 ,以Verilog硬件描述语言描述的电路为研究对象 ,提出寄存器传输级 (RTL)集成电路的静态时序深度和动态时序深度概念 .从静态、动态两方面出发度量语句的执行效果和程序运行的时序关系 ,并结合实例分析了二者在高层次测试生成中的应用 .高层次行为信息的提取也将为高层次设计和验证提供方便 .

In high-level test generation,to grasp better the structural information of high-level circuits,circuits based on Verilog hardware description language (HDL) are researched,and static sequential depth and dynamic sequential depth are introduced firstly.Executive effects of sentences and sequential relations of program are measured by static and dynamic methods,and applications in high-level test generation are analyzed instantially.In addition,behavioral information retrieval of high-level circuits will provide convenience for high-level designs and verifications.